Education Guide

1.    How timing sequences can be generated using shift registers?

Definition of Shift Registers

Shift Register is a group of flip flops set up in a linear fashion which have their inputs and outputs connected together in such a way that the data is shifted down the line when the circuit is activated.

Shift registers can have co parallel inputs and outputs, including serial-in, parallel-out (SIPO) and parallel-in, serial-out (PISO) types. There are also types that have both serial and parallel input, and types with serial and parallel output. There are also bi-directional shift registers which allow you to vary the direction of the shift register. The serial input and outputs of a register can also be connected together to create a circular shift register. One could also create multi-dimensional shift registers, which can perform more complex computation

 

Types of Shift Registers

1 SISO (Serial-in serial-out)

2 SIPO (Serial-In Parallel-Out)

3 PIPO(Parallel in Parallel Out)

One of the most common uses of a shift register is to convert between serial and parallel interfaces. This is useful as many circuits work on groups of bits in parallel, but serial interfaces are simpler to construct. Shift registers can be used as simple delay circuits. Several bi-directional shift registers could also be connected in parallel for a hardware implementation of a stack.

Shift registers can be used also as a pulse extenders. Compared to monostable multivibrators the timing has no dependency on component values, however requires external clock and the timing accuracy is limited by a granularity of this clock. Example – Ronja Twister, where five 74164 shift registers create the core of the timing logic this way (schematic).

In early computers, shift registers were used to handle data processing: two numbers to be added were stored in two shift registers and clocked out into an arithmetic and logic unit (ALU) with the result being fed back to the input of one of the shift registers (the Accumulator) which was one bit longer since binary addition can only result in an answer that is the same size or one bit longer.

Many computer languages include instructions to ’shift right’ and ’shift left’ the data in a register, effectively dividing by two or multiplying by two for each place shifted.

Very large serial-in serial-out shift registers (thousands of bits in size) were used in a similar manner to the earlier delay line memory in some devices built in the early 1970s.

 

2.    Write a short note on design of modulo-n counters.

Design of Modulo-n counters

In this section we refine an abstract specification of a modulo N counter into a non-trivial bit-level implementation. Before going through the different design steps in detail we give an overview of the entire development process. As shown in Figure we start with a black box specification MNC that characterizes the external behavior of the counter.

 

An overview about Design of Modulo-n Counter

The input lines carry streams of bits and the output line carries natural numbers between 0 and N-1. In the first design step 1 or so called structural refinement the black box specification is refined into a specification of a controller COL and a counter CNT. The controller is responsible for resetting the counter whenever the counter’s most recent output was N-1 and a new count signal is received. The counter itself increases or resets the output value on demand. In the following we restrict ourselves to the development of the counter only. The second design step 2 so called interface refinement replaces each output line which carries natural numbers by an appropriate number of output lines carrying bits. The necessary number of lines is of course a function of N.The third design step 3 is a so called action refinement. To allow hardware implementations based on master-slave flip-flops where only impulses and not signals (sequence of 1’s) are counted we have to refine the bits on the input lines in an adequate way. The interesting action refinement is the refinement of a 1 which is represented by a 1 followed by a 0, consequently a sequence of 1’s is replaced by a sequence of impulses. The fourth design step 4 is a combination of a structural and a behavioral refinement step. The specification of the counter achieved during the third design step is split into a network of identical component specifications. Each specification describes a bit-slice of the counter and could be implemented by a master-slave flip-flop. Note that the development of the modulo N counter would of course also include the corresponding refinement steps for the controller to ensure that both components the controller and the counter work properly together.

A Modulo-n counter

We start with an abstract specification of a modulo N counter. The modulo N counter has two external input channels which corresponds to the count (i₁)

and to the clear(i₂) input and one external output channel which carries natural numbers є{0,…,N-1} indicated by the Figure above. The counter counts from state 0 through state N-1 and than cycles back to state 0. Regardless of the count input a 1 at the clear input resets the counter to 0. On the other hand a 1 at the count input increments the counter with respect to modulo N. The formal specification is given in the Figure below .

 3.    Explain temperature and weather forecast system with a neat circuit diagram.

Temperature and Weather Forecast Systems

 

Assumptions/Design Criteria:

 

• · The barometer will be operated indoors. This will minimize output variations caused by temperature and will    lengthen the    calibration intervals. It also means the circuit board will not have to be weatherproofed.
• · Will be easy to calibrate. This means there will be a maximum of 1 calibration adjustment.
• · The operating range will be from 28.00 inHg to 32.00 inHg
• · Resolution will be greater than .01 inHg from sea level to 10,000 feet.
• · The interface will be standard Dallas Semiconductor 1-wire.
• · Because the unit will be designed for indoor operation, it can be externally powered.
• · Will utilize the Motorola MPX4115A pressure transducer.

Based on these assumptions, table 1 was generated. This table calculates the station pressure for both the minimum (28.00) and the maximum (32.00) pressures for altitudes from sea level to 10,000 feet in 1000 foot increments. The station pressure is then converted to MPX4115A pressure sensor volts. Looking at the table, I discovered the predominant change in altitude in the offset voltage of the pressure sensor. I decided that this will be the adjustable parameter, and that the circuit gain would be fixed.

 

The OA Offset column is the op amp offset voltage that compensates for altitude. This will be the only calibration variable. Since the instrumentation amplifier is a rail-to-rail device, in theory it will operate down to 0 volts. However, to provide some margin, the offsets were chosen to allow a minimum of .2 volts at the lowest pressure. The gain of 10 was chosen to allow maximum output voltage swing for all altitudes. The resulting op amp output voltages are listed in OA Output column. This is the voltage applied to the DS2438 Vad input.

 

Circuit Design:

The following circuit design satisfies these requirements. I selected the INA122 instrumentation amp for several reasons: it eliminated several external resistors and it provides a very stable gain over a wide temperature. It also provides excellent rail-to-rail operation allowing full use of the 10 volt input range of the DS2438. The 40.2K ohm resistor sets the gain to 10. The variable resistor allows adjustment of the offset voltage from 2.0v to 4.0v. All parts are available from Digikey except the pressure sensor, which is available from Newark.

 

Calibration:

Hardware calibration is simply a matter of setting the offset voltage to the value listed in table 1 for your altitude. A jumper on the input of the DS2438 allows the use of the DS2438 to measure the offset. Put the jumper in the A-C position and using the iButton Viewer for the DS2438, set the voltage to the table value using the 25-turn pot. Once it’s set, put the jumper in the A-B position to read pressure.

For altitudes in between the values listed in the table, simple interpolation will give accurate results. An Excel spreadsheet will be also available online to calculate intermediate values.

 

Software:

Routines currently exist to measure the DS2438s Vad voltage. Once this voltage is measured, the pressure is calculated using:

Press = slope * Vad + intercept

Where the slope and intercept are the values listed in table 1 for your altitude. The prototype code I used had an external text file to store the slope and intercept values.

This allows the user to edit the file to fine-tune the calibration if desired.

 

Fine-tuning can be accomplished by monitoring the pressure and comparing it with a known reference source, such as a nearby airport or NOAA weather. Start by adjusting the intercept. When the reference station indicates a pressure near mid-scale (30.00 inHg), adjust the software intercept value until your weather station matches. Now monitor the pressure extremes to determine if the slope needs adjustment. An Excel spreadsheet will be available as an aid.

4.    Explain the working of MODEM.

MODEM

Modem (from modulator-demodulator) is a device that modulates an analog carrier signal to encode digital information, and also demodulates such a carrier signal to decode the transmitted information. The goal is to produce a signal that can be transmitted easily and decoded to reproduce the original digital data. Modems can be used over any means of transmitting analog signals, from driven diodes to radio.

 

The most familiar example is a voiceband modem that turns the digital 1s and 0s of a personal computer into sounds that can be transmitted over the telephone lines of Plain Old Telephone Systems (POTS), and once received on the other side, converts those 1s and 0s back into a form used by a USB, Ethernet, serial, or network connection. Modems are generally classified by the amount of data they can send in a given time, normally measured in bits per second, or “bps”. They can also be classified by Baud, the number of times the modem changes its signal state per second.

 

List of dialup speeds

Note that the values given are maximum values, and actual values may be slower under certain conditions (for example, noisy phone lines). For a complete list see the companion article List of device bandwidths.

 

Radio modems

 

Direct broadcast satellite, WiFi, and mobile phones all use modems to communicate, as do most other wireless services today. Modern telecommunications and data networks also make extensive use of radio modems where long distance data links are required. Such systems are an important part of the PSTN, and are also in common use for high-speed computer network links to outlying areas where fibre is not economical.

 

Wireless modems come in a variety of types, bandwidths, and speeds. Wireless modems are often referred to as transparent or smart. They transmit information that is modulated onto a carrier frequency to allow many simultaneous wireless communication links to work simultaneously on different frequencies.

 

Smart modems come with a media access controller inside which prevents random data from colliding and resends data that is not correctly received. Smart modems typically require more bandwidth than transparent modems, and typically achieve higher data rates. The IEEE 802.11 standard defines a short range modulation scheme that is used on a large scale throughout the world.

 

WiFi and WiMax

 

Wireless data modems are used in the WiFi and WiMax standards, operating at microwave frequencies.

 

WiFi (Wireless Fidelity) is principally used in laptops for Internet connections (wireless access point) and wireless application protocol (WAP).

 

 Mobile modems & routers

 

Modems which use mobile phone lines (GPRS,UMTS,HSPA,EVDO,WiMax,etc.), are known as Cellular Modems. Cellular modems can be embedded inside a laptop or appliance, or they can be external to it. External cellular modems are datacards and cellular routers. The datacard is a PC card or ExpressCard which slides into a PCMCIA/PC card/ExpressCard slot on a computer. The most famous brand of Radio modem datacards is the AirCard made by Sierra Wireless. (Many people just refer to all makes and models as “AirCards”, when in fact this is a trademarked brand name.) Nowadays, there are USB cellular modems as well that use a USB port on the laptop instead of a PC card or ExpressCard slot. A cellular router may or may not have an external datacard (“AirCard”) that slides into it. Most cellular routers do allow such datacards or USB modems, except for the WAAV, Inc. CM3 mobile broadband cellular router. Cellular Routers may not be modems per se, but they contain modems or allow modems to be slid into them..

 

Most of the GSM cellular modems come with an integrated SIM cardholder (i.e, Huawei E220, Sierra 881, etc.) The CDMA (EVDO) versions do not use SIM cards, but use ESN (Electronic Serial Numbers) instead.

 

The cost of using a cellular modem varies from country to country. Some carriers implement “flat rate” plans for unlimited data transfers. Some have caps (or maximum limits) on the amount of data that can be transferred per month. Other countries have “per Megabyte” or even “per Kilobyte” plans that charge a fixed rate per Megabyte or Kilobyte of data downloaded; this tends to add up quickly in today’s content-filled world, which is why many people are pushing for flat data rates. See : flat rate.

 

The faster data rates of the newest cellular modem technologies (UMTS,HSPA,EVDO,WiMax) are also considered to be “Broadband Cellular Modems” and compete with other Broadband modems below.

 

Broadband, DSL modem

 

ADSL modems, a more recent development, are not limited to the telephone’s “voiceband” audio frequencies. Some ADSL modems use coded orthogonal frequency division modulation (DMT).

 

Cable modems use a range of frequencies originally intended to carry RF television channels. Multiple cable modems attached to a single cable can use the same frequency band, using a low-level media access protocol to allow them to work together within the same channel. Typically, ‘up’ and ‘down’ signals are kept separate using frequency division multiple access.

 

New types of broadband modems are beginning to appear, such as doubleway satellite and power line modems.

 

Broadband modems should still be classed as modems, since they use complex waveforms to carry digital data. They are more advanced devices than traditional dial-up modems as they are capable of modulating/demodulating hundreds of channels simultaneously.

 

Many broadband modems include the functions of a router (with Ethernet and WiFi ports) and other features such as DHCP, NAT and firewall features.

 

When broadband technology was introduced, networking and routers were unfamiliar to consumers. However, many people knew what a modem was as most internet access was through dial-up. Due to this familiarity, companies started selling broadband modems using the familiar term “modem” rather than vaguer ones like “adapter” or “transceiver”.

 

Many broadband modems must be configured in bridge mode before they can use a router.

 

Deep-space telecommunications

 

Many modern modems have their origin in deep space telecommunications systems of the 1960s. Differences with deep space telecom modems vs landline modems digital modulation formats that have high doppler immunity are typically used waveform complexity tends to be low, typically binary phase shift keying error correction varies mission to mission, but is typically much stronger than most landline modems

 

Voice modem

 

Voice modems are regular modems that are capable of recording or playing audio over the telephone line. They are used for telephony applications. See Voice modem command set for more details on voice modems. This type of modem can be used as FXO card for Private branch exchange systems (compare V.92).

5.    Write a short note on ADC.

A direct conversion ADC or flash ADC has a bank of comparators, each firing for their decoded voltage range. The comparator bank feeds a logic circuit that generates a code for each voltage range. Direct conversion is very fast, but usually has only 8 bits of resolution (255 comparators – since the number of comparators required is 2n – 1) or fewer, as it needs a large, expensive circuit. ADCs of this type have a large die size, a high input capacitance, and are prone to produce glitches on the output (by outputting an out-of-sequence code). Scaling to newer submicron technologies does not help as the device mismatch is the dominant design limitation. They are often used for video, wideband communications or other fast signals in optical storage.

 

A successive-approximation ADC uses a comparator to reject ranges of voltages, eventually settling on a final voltage range. Successive approximation works by constantly comparing the input voltage to the output of an internal digital to analog converter (DAC, fed by the current value of the approximation) until the best approximation is achieved. At each step in this process, a binary value of the approximation is stored in a successive approximation register (SAR). The SAR uses a reference voltage (which is the largest signal the ADC is to convert) for comparisons. For example if the input voltage is 60 V and the reference voltage is 100 V, in the 1st clock cycle, 60 V is compared to 50 V (the reference, divided by two. This is the voltage at the output of the internal DAC when the input is a ‘1′ followed by zeros), and the voltage from the comparator is positive (or ‘1′) (because

60 V is greater than 50 V). At this point the first binary digit (MSB) is set to a ‘1′. In the 2nd clock cycle the input voltage is compared to 75 V (being halfway between 100 and 50 V: This is the output of the internal DAC when its input is ‘11′ followed by zeros) because 60 V is less than 75 V, the comparator output is now negative (or ‘0′). The second binary digit is therefore set to a ‘0′. In the 3rd clock cycle, the input voltage is compared with 62.5 V (halfway between 50 V and 75 V: This is the output of the internal DAC when its input is ‘101′ followed by zeros). The output of the comparator is negative or ‘0′ (because 60 V is less than 62.5 V) so the third binary digit is set to a 0. The fourth clock cycle similarly results in the fourth digit being a ‘1′ (60 V is greater than 56.25 V, the DAC output for ‘1001′ followed by zeros). The result of this would be in the binary form 1001. This is also called bit-weighting conversion, and is similar to a binary search. The analogue value is rounded to the nearest binary value below, meaning this converter type is mid-rise (see above). Because the approximations are successive (not simultaneous), the conversion takes one clock-cycle for each bit of resolution desired. The clock frequency must be equal to the sampling frequency multiplied by the number of bits of resolution desired. For example, to sample audio at 44.1 kHz with 32 bit resolution, a clock frequency of over 1.4 MHz would be required. ADCs of this type have good resolutions and quite wide ranges. They are more complex than some other designs.

 

A ramp-compare ADC (also called integrating, dual-slope or multi-slope ADC) produces a saw-tooth signal that ramps up, then quickly falls to zero. When the ramp starts, a timer starts counting. When the ramp voltage matches the input, a comparator fires, and the timer’s value is recorded. Timed ramp converters require the least number of transistors. The ramp time is sensitive to temperature because the circuit generating the ramp is often just some simple oscillator. There are two solutions: use a clocked counter driving a DAC and then use the comparator to preserve the counter’s value, or calibrate the timed ramp. A special advantage of the ramp-compare system is that comparing a second signal just requires another comparator, and another register to store the voltage value. A very simple (non-linear) ramp-converter can be implemented with a microcontroller and one resistor and capacitor. Vice versa a filled capacitor can be taken from an integrator, time-to-amplitude converter, phase detector, sample and hold circuit, or peak and hold circuit and discharged. This has the advantage that a slow comparator cannot be disturbed by fast input changes.

 

A pipeline ADC (also called subranging quantizer) uses two or more steps of subranging. First, a coarse conversion is done. In a second step, the difference to the input signal is determined with a digital to analog converter (DAC). This difference is then converted finer, and the results are combined in a last step. This can be considered a refinement of the successive approximation ADC wherein the feedback reference signal consists of the interim conversion of a whole range of bits (for example, four bits) rather than just the next-most-significant bit. By combining the merits of the successive approximation and flash ADCs this type is fast, has a high resolution, and only requires a small die size.

 

A Sigma-Delta ADC (also known as a Delta-Sigma ADC) oversamples the desired signal by a large factor and filters the desired signal band. Generally a smaller number of bits than required are converted using a Flash ADC after the Filter. The resulting signal, along with the error generated by the discrete levels of the Flash, is fed back and subtracted from the input to the filter. This negative feedback has the effect of noise shaping the error due to the Flash so that it does not appear in the desired signal frequencies. A digital filter (decimation filter) follows the ADC which reduces the sampling rate, filters off unwanted noise signal and increases the resolution of the output. (sigma-delta modulation, also called delta-sigma modulation)

 

6. Draw and explain the operation of parallel-in-parallel-out shift register.

 

PIPO(Parallel in Parallel Out)

The purpose of the parallel-in/ parallel-out shift register is to take in parallel data, shift it, then output it as shown below. A universal shift register is a do-everything device in addition to the parallel-in/ parallel-out function.

 

Above we apply four bit of data to a parallel-in/parallel-out shift register at DA DB DC DD. The mode control, which may be multiple inputs, controls parallel loading vs shifting. The mode control may also control the direction of shifting in some real devices. The data will be shifted one bit position for each clock pulse. The shifted data is available at the outputs QA QB QC QD. The “data in” and “data out” are provided for cascading of multiple stages. Though, above, we can only cascade data for right shifting. We could accommodate cascading of left-shift data by adding a pair of left pointing signals, “data in” and “data out”, above.

The internal details of a right shifting parallel-in/ parallel-out shift register are shown below. The tri-state buffers are not strictly necessary to the parallel-in/ parallel-out shift register, but are part of the real-world device shown below.

 

The 74LS395 so closely matches our concept of a hypothetical right shifting parallel-in/ parallel-out shift register that we use an overly simplified version of the data sheet details above. See the link to the full data sheet with more details, later in this chapter

LD/SH’ controls the AND-OR multiplexer at the data input to the FF’s. If LD/SH’=1, the upper four AND gates are enabled allowing application of parallel inputs DA DB DC DD to the four FF data inputs. Note the inverter bubble at the clock input of the four FFs. This indicates that the 74LS395 clocks data on the negative going clock, which is the high to low transition. The four bits of data will be clocked in parallel from DA DB DC DD to QA QB QC QD at the next negative going clock. In this “real part”, OC’ must be low if the data needs to be available at the actual output pins, as opposed to only on the internal FFs.

 

 

 

7. Design the counter that goes through states 0, 1, 2, 4, 0…using D flip-flops

 

There is one caveat that must be considered here: The 5-stage circuit uses five flip-flops, and therefore has 32 possible binary states, yet we only use ten states. The 4-stage counter uses only eight of 16 possible states. We must include circuitry that will filter out the illegal states and force this circuit to go towards the correct counting sequence, even if it finds itself in an illegal mode when first powered up. This is not difficult, and the demonstration circuit below includes the necessary gating structure.
The circuit below is logically equivalent to the CMOS 4017 decimal counter, although slightly simplified from the commercial unit.

The demonstration above initially implements only the legitimate counting sequence of the Johnson counter. To allow for all possible illegal combinations and show how they get straightened out, we would need 66 separate images for the overlays, and each image is about 6.5K bytes in size. That’s a bit much to ask of many users.

However, you can see the count correction gates operating at the bottom of the counter, and see how they work. The D